1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor device upon forming a film on the surface of a substrate formed with concave portions, and a semiconductor manufacturing apparatus.
2. Description of Related Art
In recent semiconductor devices, delay in signal transmission along interconnections restricts the device operation. The delay constant along the interconnections is represented by a product of an interconnect resistance and an inter-interconnect capacitance, and Cu of low electrical resistivity value has been used usually for interconnection materials in order to lower the interconnect resistance and increase the device operation speed.
A Cu multi-layered interconnection is formed by a damascene method. The damascene method includes a deposition step for an insulative film such as an inter-layer insulative film, a step of forming concave portions (interconnection trenches in a case of an interconnection layer or via holes in a case of via), a barrier metal deposition step, a deposition step for a thin Cu film referred to as a Cu seed, a burying step by Cu deposition using the thin Cu film as a cathode electrode for electrolytic plating, a step of removing the barrier metal and Cu deposited to the outside of the concave portions by chemical mechanical polishing (CMP), and a barrier insulative film deposition step.
In a case where holes referred to as voids are present in the Cu interconnection, since electrical properties (such as resistance, reliability, yield, etc.) are deteriorated, burying with no voids is important in Cu plating. The deposition speed in Cu plating is high near and at the bottom of the opening of the concave portion for the opening. In a case where the opening of the concave portion is closed by the lateral growing near the opening before film formation from the bottom surface reaches the upper end of the opening of the concave portion, voids are left in the film. On the other hand, in a case where the bottom surface reaches the upper end of the opening before closure of the opening, voidless Cu plating burying can be attained. Sine the voidless burying is easier as the opening is wider, a thinner film thickness for the Cu seed is more preferred and it tends to be thinner along with shrink of feature size. In recent years, it has been investigated to directly apply Cu plating on a barrier metal using the barrier metal as a seed with no deposition of the Cu seed. Among all, Ru of good adhesion with Cu has been noted as the barrier metal.
Non-patent document 1 discloses that removal of a native oxide film on Ru is important for the Cu plating film formation on the Ru seed, and satisfactory Cu film formation can be attained by reducing with deaerated sulfuric acid. Non-patent document 2 discloses that the Cu plating film formation on Ru is improved by the use of a Pd catalyst.
Patent document 1 discloses a method of detecting the instance the surface of a metal plating film is planarized by the change of the reflectance and forming the surface planar with no pattern dependency. Further, Patent documents 2 to 4 disclose means for controlling or measuring the plating thickness by measuring the presence or absence of a reflection light or the intensity of the reflection light at the plated surface.    [Patent document 1] Japanese Patent-Laid Open Publication No. 2000-315663    [Patent document 2] Japanese Patent-Laid Open Publication No. 2000-204498    [Patent document 3] Japanese Patent-Laid Open Publication No. 05(1993)-186898    [Patent document 4] Japanese Patent-Laid Open Publication No. 2005-307274    [Non-patent document 1] T. P. Moffat et. al., J. Electrochem, Soc. 153(1), C37-C50 (2006)    [Non-patent document 2] Sung Ki Cho et. al., J. Vac. Sci. Technol. B 22(6), 2004, pp. 2649-2653
However, the related arts described in the documents above still leave room for improvement with respective to the following points.
The subject in the related art includes that a recipe has to be prepared for every product in accordance with its surface area of the film to be formed. In a case where the surface area is different on every wafer or product, the number of recipes increases to result in complexity and a burden on recipe control increases. Specifically, the number of recipes to be controlled in apparatus increases, which increases the control burden in a factory of specifying a recipe to the apparatus while judging products.
For example, the Cu plating film formation proceeds in the order of forming growing nuclei (hereinafter simply referred to as nuclei) on a seed, coalescence of nuclei, and formation of a continuous film. Under the condition where nuclei are difficult to be formed and the in-plane density of nuclei is low, growing proceeds isometrically around the nuclei as the center, a gap is formed between nuclei to be coalesced to result in a coarse film. Accordingly, it is desirable that the in-plane density of nuclei is high. The nuclei forming density increases along with increase in the current density and is saturated at a current density of a certain level or higher (hereinafter the current density is referred to as a saturation current density). That is, a coarse film is formed unless the current density is higher than the saturation current density. On the other hand, in a case where the current density is excessively high, hydrogen is generated to result in a problem such as increase in the fragility of a plating film. Accordingly, it is necessary to control the plating current density to higher than the saturation current density and lower than a hydrogen generating current density.
By the way, the dimension and the density of the concave portions change on every product and, correspondingly, the surface area of the seed also changes. This is because it is desired that the seed film is formed conformably corresponding to the unevenness on the surface. While the change of the surface area tends to increase along with shrink of feature size, it is up to about 5 times at the maximum in the 32 nm generation relative to a blanket film formed on a bare wafer. In a case where the surface area increases for an identical current value, the current density possibly lowers to below the saturation current density. On the contrary, in a case where the surface area decreases for an identical current value, the current density possibly increases to higher than the hydrogen generating current density. In the prior arts described in the documents above, since the current value for each of the steps has no relation with the reflectance, it cannot cope with the change of the surface area due to the change of the pattern to sometimes result in film formation failure such as burying failure.
In patent document 1, since burying is confirmed by measuring the reflectance after plating film formation, it cannot cope with the change of the surface area due to the change of the pattern for the concave portions. In the same manner, since patent documents 2 to 4 also monitor the plating thickness or the like by measuring the reflectance at the plated surface after plating film formation, they cannot cope with the change of the surface area on every wafer.
Accordingly, in such documents, it is necessary to prepare a different recipe in accordance with every product.